IDT72421L12(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L12
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

WCLK

D0 - D8

WEN1

tDS

tENS

D1

D0 (First Valid

WEN2

(If Applicable)

RCLK

EF

tSKEW1

tFRL (1)

tREF

MILITARY AND COMMERCIAL TEMPERATURE RANGES

D2

D3

REN1,

REN2

Q0 - Q8

OE

tA

tOLZ

tOE

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 7. First Data Word Latency Timing

tA

D0

D1

2655 drw 09

5.07

12

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