IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
WCLK
WEN1
WEN2
(If Applicable)
tCLKH
tCLKL
tENS
tENH
tENS
tENH
PAE
RCLK
n words in FIFO
tSKEW2(2)
(1)
tPAE
REN1,
REN2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
n+1 words in FIFO
tPAE
(3)
tENS tENH
2655 drw 13
NOTES:
1. PAE offset = n.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
5.07
16