IDT72421L10(2017) データシートの表示（PDF） - Integrated Device Technology
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IDT72421L10
(Rev.:2017)
(Rev.:2017)
Integrated Device Technology
IDT72421L10 Datasheet PDF : 14 Pages
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IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72421/72201/72211/72221/72231/72241/72251 may be used
when the application requirements are for 64/256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should be created for each
of the endpoint status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72421/72201/72211/72221/72231/72241/72251s.
Any word width can be attained by adding additional IDT72421/72201/72211/
72221/72231/72241/72251s.
When these FIFOs are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/
72251 can be adapted to applications when the requirements are for greater
than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two
enable pins on the read and write port allow depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth expansion
configuration thus the Programmable flags are set to the default values. Depth
expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A
typical application would have the expansion logic alternate data access from
one device to the next in a sequential manner. These devices operate in the
Depth Expansion configuration when the following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a
second Write Enable.
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D0 - D8)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)
RESET (RS)
IDT
72421
72201
72211
72221
72231
72241
72251
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
DATA OUT (Q0 - Q8)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ ENABLE 2 (REN2)
2655 drw 16
Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO
RESET (RS)
DATA IN (D)
18
9
WRITE CLOCK (WCLK)
WRITE ENABLE1 (WEN1)
WRITE ENABLE2/LOAD (WEN2/LD)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
PROGRAMMABLE (PAF)
IDT
72421
72201
72211
72221
72231
72241
72251
9
9
RESET (RS)
IDT
72421
72201
72211
72221
72231
72241
72251
READ CLOCK (RCLK)
READ ENABLE1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9 DATA OUT (Q)
18
READ ENABLE 2 (REN2)
READ ENABLE 2 (REN2)
2655 drw 17
Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
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