V53C8258HP40 データシートの表示（PDF） - Mosel Vitelic Corporation

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V53C8258HP40

HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic Corporation  

MOSEL VITELIC

Functional Description

The V53C8258H is a CMOS dynamic RAM

optimized for high data bandwidth, low power

applications. It is functionally similar to a traditional

dynamic RAM. The V53C8258H reads and writes

data by multiplexing an 18-bit address into a 9-bit

row and a 9-bit column address. The row address is

latched by the Row Address Strobe (RAS). The

column address “flows through” an internal address

buffer and is latched by the Column Address Strobe

(CAS). Because access time is primarily dependent

on a valid column address rather than the precise

time that the CAS edge occurs, the delay time from

RAS to CAS has little effect on the access time.

Memory Cycle

A memory cycle is initiated by bringing RAS low.

Any memory cycle, once initiated, must not be

ended or aborted before the minimum tRAS time has

expired. This ensures proper device operation and

data integrity. A new cycle must not be initiated until

the minimum precharge time tRP/tCP has elapsed.

Read Cycle

A Read cycle is performed by holding the Write

Enable (WE) signal High during a RAS/CAS

operation. The column address must be held for a

minimum specified by tAR. Data Out becomes valid

only when tOAC, tRAC, tCAA and tCAC are all satisifed.

As a result, the access time is dependent on the

timing relationships between these parameters. For

example, the access time is limited by tCAA when

tRAC, tCAC and tOAC are all satisfied.

Write Cycle

A Write Cycle is performed by taking WE and

CAS low during a RAS operation. The column

address is latched by CAS. The Write Cycle can be

WE controlled or CAS controlled depending on

whether WE or CAS falls later. Consequently, the

input data must be valid at or before the falling edge

of WE or CAS, whichever occurs last. In the CAS-

V53C8258H

controlled Write Cycle, when the leading edge of

WE occurs prior to the CAS low transition, the I/O

data pins will be in the High-Z state at the beginning

of the Write function. Ending the Write with RAS or

CAS will maintain the output in the High-Z state.

In the WE controlled Write Cycle, OE must be in

the high state and tOED must be satisfied.

Extended Data Output Page Mode

EDO Page operation permits all 512 columns

within a selected row of the device to be randomly

accessed at a high data rate. Maintaining RAS low

while performing successive CAS cycles retains the

row address internally and eliminates the need to

reapply it for each cycle. The column address buffer

acts as a transparent or flow-through latch while

CAS is high. Thus, access begins from the

occurrence of a valid column address rather than

from the falling edge of CAS, eliminating tASC and tT

from the critical timing path. CAS latches the

address into the column address buffer. During

EDO operation, Read, Write, Read-Modify-Write or

Read-Write-Read cycles are possible at random

addresses within a row. Following the initial entry

cycle into Hyper Page Mode, access is tCAA or tCAP

controlled. If the column address is valid prior to the

rising edge of CAS, the access time is referenced to

the CAS rising edge and is specified by tCAP. If the

column address is valid after the rising CAS edge,

access is timed from the occurrence of a valid

address and is specified by tCAA. In both cases, the

falling edge of CAS latches the address and

enables the output.

EDO provides a sustained data rate of 71 MHz for

applications that require high bandwidth such as

bit-mapped graphics or high-speed signal

processing. The following equation can be used to

calculate the maximum data rate:

Data Rate =

512

tRC + 511 x tPC

V53C8258H Rev. 1.4 February 1997

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