IDTCV122C データシートの表示（PDF） - Integrated Device Technology

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IDTCV122C

PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV122C

PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONT.)

Pin Number

Name

Type

47

SCL

IN

48

VDD_REF

PWR

49

XTAL_OUT

OUT

50

XTAL_IN

IN

51

VSS_REF

GND

52

FS_C/REF0

I/O

53

VDD_Suspend

PWR

54

FS_A(REF1/PCI5)

I/O

55

PCI0

OUT

56

PCI1

OUT

Description

SM Bus CLK

3.3V

XTAL output

XTAL input

GND

CPU frequency selection input at VTT_PWRGD assertion. 14.318 reference clock output afterward.

Keep supply 3.3V in the power down

CPU frequency selection input at VTT_PWRGD assertion. 14.318 reference clock output or PCI clock,

programmed through SMBus Register Byte 1.

PCI clock

PCI clock

INDEX BLOCK WRITE PROTOCOL

Bit

# of bits

From

Description

1

1

Master

Start

2-9

8

Master

D2h

10

1

Slave

Ack (Acknowledge)

11-18

8

Master

Register offset byte (starting byte)

19

1

Slave

Ack (Acknowledge)

20-27

8

Master

Byte count, N (0 is not valid)

28

1

Slave

Ack (Acknowledge)

29-36

8

Master

first data byte (Offset data byte)

37

1

Slave

Ack (Acknowledge)

38-45

8

Master

2nd data byte

46

1

Slave

Ack (Acknowledge)

:

Master

Nth data byte

Slave

Acknowledge

Master

Stop

INDEX BLOCK READ PROTOCOL

Master can stop reading any time by issuing the Stop bit without waiting

until N byte (byte count bit 30-37).

Bit

# of bits

From

Description

1

1

Master

Start

2-9

8

Master

D2h

10

1

Slave

Ack (Acknowledge)

11-18

8

Master

Register offset byte (starting byte)

19

1

Slave

Ack (Acknowledge)

20

1

Master

Repeated Start

21-28

8

Master

D3h

29

1

Slave

Ack (Acknowledge)

30-37

8

Slave

Byte count, N (Byte 8)

38

1

Master

Ack (Acknowledge)

39-46

8

Slave

first data byte (Offset data byte)

47

1

Master

Ack (Acknowledge)

48-55

8

Slave

2nd data byte

Ack (Acknowledge)

:

Master

Ack (Acknowledge)

Slave

Nth data byte

Not acknowledge

Master

Stop

INDEX BYTE WRITE

Setting bit[11:18] = starting address, bit[20:27] = 01h.

INDEX BYTE READ

Setting bit[11:18] = starting address. After reading back the first data byte,

master issues Stop bit.

4

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