IDTCV123 データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDTCV123

PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV123

PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

BYTE 8

Bit

7

6

5

4

3

2

1

0

Output(s) Affected

SRC SSC enable

USB48

Reserve

One cycle read

Description / Function

Only valid when Byte1 bit0 is 1

CPU PLL power down

SRC PLL power down

USB PLL power down

USB 48 Strength control

N Programming enable

0

disable

normal

normal

normal

1x

Disable

disable

COMMERCIAL TEMPERATURE RANGE

1

enable

Power down

Power down

Power down

2x

enable

enable

Type

Power On

RW

1

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

BYTE 9

Bit

7

6

5

4

3

2

1

0

Output(s) Affected

CPU SMC2

CPU SMC1

CPU SMC0

Reserve

SRC SMC2

SRC SMC1

SRC SMC0

Description / Function

Must be 0

see SMC table

CPU PLL SSC control

see SMC table

SRC/PCI SSC control

0

Must be 0

1

Type

Power On

RW

0

(Must be 0)

RW

0

RW

0

RW

1

RW

0

RW

0

RW

0

RW

1

BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.

BYTE 17

Bit

Output(s) Affected

Description / Function

0

1

Type

Power On

7

CPU_N7, MSB

RW

6

CPU_N6

RW

5

CPU_N5

RW

4

CPU_N4

RW

3

CPU_N3

RW

2

CPU_N2

RW

1

CPU_N1

see Resolution table

RW

0

CPU_N0, LSB

CPU CLK = N* Resolution

RW

BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.

8

Share Link: