IDT82V3355 データシートの表示（PDF） - Integrated Device Technology
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IDT82V3355 Datasheet PDF : 135 Pages
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IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31
3.10.1.5 Holdover Mode ................................................................................................................................................................. 31
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32
3.10.1.5.4 Manual ........................................................................................................................................................... 32
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 32
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 32
3.10.2.2 Locked Mode .................................................................................................................................................................... 32
3.10.2.3 Holdover Mode ................................................................................................................................................................. 32
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 34
3.11.1 PFD Output Limit ............................................................................................................................................................................ 34
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 34
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 34
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 34
3.11.5.1 T0 Path ............................................................................................................................................................................. 34
3.11.5.2 T4 Path ............................................................................................................................................................................. 35
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 36
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 36
3.13.1 Output Clocks ................................................................................................................................................................................. 36
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39
3.14 INTERRUPT SUMMARY ............................................................................................................................................................................... 41
3.15 T0 AND T4 SUMMARY ................................................................................................................................................................................. 41
3.16 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 42
3.17 LINE CARD APPLICATION .......................................................................................................................................................................... 43
4 MICROPROCESSOR INTERFACE .................................................................................................................................. 44
5 JTAG ................................................................................................................................................................................ 46
6 PROGRAMMING INFORMATION .................................................................................................................................... 47
6.1 REGISTER MAP ............................................................................................................................................................................................ 47
6.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 52
6.2.1 Global Control Registers ............................................................................................................................................................... 52
6.2.2 Interrupt Registers ......................................................................................................................................................................... 59
6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 63
6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 74
6.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 85
6.2.6 T0 / T4 DPLL State Machine Control Registers ........................................................................................................................... 89
6.2.7 T0 / T4 DPLL & APLL Configuration Registers ............................................................................................................................ 91
6.2.8 Output Configuration Registers .................................................................................................................................................. 104
6.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 108
6.2.10 Synchronization Configuration Registers ................................................................................................................................. 110
7 THERMAL MANAGEMENT ........................................................................................................................................... 112
7.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 112
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 112
7.3 HEATSINK EVALUATION .......................................................................................................................................................................... 112
8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 113
8.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 113
8.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 113
8.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 114
8.3.1 CMOS Input / Output Port ............................................................................................................................................................ 114
8.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 115
Table of Contents
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May 19, 2009
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