INTEL387TMDX データシートの表示（PDF） - Intel

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INTEL387TMDX

Intel387™ DX MATH COPROCESSOR

Intel 

Intel387TM DX MATH COPROCESSOR

NOTE

1 Cycles between operand write to the MCP and storing result

Figure 3 7 Pipelined Cycles with Wait States

240448 – 12

240448 – 13

NOTES

1 Instruction dependent

2 PEREQ is an asynchronous input to the Intel386TM DX Microprocessor it may not be asserted (instruction depen-

dent)

3 More operand transfers

4 Memory read (operand) cycle is not shown

Figure 3 8 STEN BUSY and PEREQ Timing Relationship

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