IP1000ALF-DS-R01 データシートの表示（PDF） - Unspecified

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IP1000ALF-DS-R01

Gigabit Ethernet NIC Single Chip

Unspecified 

IP1000A LF

Preliminary Data Sheet

The IP1000A LF supports all of the PCI memory commands and decides on a burst-by-burst basis to

issue which command to use in order to maximize bus efficiency. The list of PCI memory commands

used by the IP1000A LF is shown below. For all commands, read and write commands are with respect

to the IP1000A LF (i.e. read implies the IP1000A LF obtains information from an off-chip location, write

implies the IP1000A LF sends information to an offchip location).

Memory Read (MR)

Memory Read Line (MRL)

Memory Read Multiple (MRM)

Memory Write (MW)

Memory Write Invalidate (MWI)

MR is used for all fetches of descriptor information. For reads of transmit frame data, MR, MRL, or MRM

is used, depending upon the remaining number of bytes in the fragment, the amount of free space in the

Transmit FIFO, and whether the Receive DMA Logic is requesting a bus master operation.

MW is used for all descriptor writes. Writes of receive frame data use either MW or MWI, depending upon

the remaining number of bytes in the fragment, the amount of frame data in the Receive FIFO, and

whether the Transmit DMA Logic is requesting a bus master operation.

The IP1000A LF provides two configuration bits to control the use of advanced memory commands. The

MwlEnable bit in the ConfigCommand register allows the host to enable or disable the use of MWI. The

MWIDisable bit in the DMACtrl register allows the host system the ability to disable the use of MWI PCI

command.

The IP1000A LF provides a set of registers that control the PCI burst behavior. These registers allow a

trade-off to be made between PCI bus efficiency and underrun/overrun frequency.

In support of bus isolation requirements for system states in which the IP1000A LF is powered down, all

IP1000A LF PCI outputs will enter the tri-state condition when the RSTN is active.

2.2.1 Reset

When the host system issues a reset to the IP1000A LF via the AsicCtrl register, a delay of at least 5ms

is required before any register access should be attempted.

2.2.2 FIFOs

The IP1000A LF uses a single configurable 32KB single-port SRAM for both the transmit and receive

FIFOs.

2.2.3 DMA

The IP1000A LF implements scatter gather Direct Memory Access (DMA) for moving data from the

IP1000A LF to/from the host’s system memory. Two independent DMA processes are used to transfer

transmit data from host system memory to the IP1000A LF (transmit DMA), and to transfer receive data

from the IP1000A LF to host system memory (receive DMA).

2.2.3.1 Transmit DMA

To utilize the IP1000A LF to transmit data onto a Gigabit Ethernet network, the data to be transmitted

must be transferred from the host’s system memory to the IP1000A LF. The data bus utilized by the

IP1000A LF for this data transfer is the PCI bus, and the method for transferring the data is DMA. The

locations within system memory which contain the data to be transmitted are indicated to the IP1000A LF

using Transmit Frame Descriptors.

Copyright © 2005, IC Plus Corp.

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July 5, 2005

IP1000A LF-DS-R08

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