INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

240187 – 14

x x x x I O Ports Accessible 2 9 12 13 15 20 24 27 33 34 40 41 48 50 52 53 58 60 62 63 96 127

Figure 4 9 Sample I O Permission Bit Map

CALL GATES

Gates provide protected indirect CALLs One of the

major uses of gates is to provide a secure method of

privilege transfers within a task Since the operating

system defines all of the gates in a system it can

ensure that all gates only allow entry into a few trust-

ed procedures

TASK SWITCHING

A very important attribute of any multi-tasking multi-

user operating system is its ability to rapidly switch

between tasks or processes The Intel386 SX Micro-

processor directly supports this operation by provid-

ing a task switch instruction in hardware The task

switch operation saves the entire state of the ma-

chine (all of the registers address space and a link

to the previous task) loads a new execution state

performs protection checks and commences execu-

tion in the new task Like transfer of control by

gates the task switch operation is invoked by exe-

cuting an inter-segment JMP or CALL instruction

which refers to a Task State Segment (TSS) or a

task gate descriptor in the GDT or LDT An INT n

instruction exception trap or external interrupt may

also invoke the task switch operation if there is a

task gate descriptor in the associated IDT descriptor

slot

The TSS descriptor points to a segment (see Figure

4 8) containing the entire execution state A task

gate descriptor contains a TSS selector The

Intel386 SX Microprocessor supports both the

80286 and Intel386 SX CPU TSSs The limit of a

Intel386 SX Microprocessor TSS must be greater

than 64H (2BH for an 80286 TSS) and can be as

large as 16 megabytes In the additional TSS space

the operating system is free to store additional infor-

mation such as the reason the task is inactive time

the task has spent running or open files belonging

to the task

Each task must have a TSS associated with it The

current TSS is identified by a special register in the

Intel386 SX Microprocessor called the Task State

Segment Register (TR) This register contains a se-

lector referring to the task state segment descriptor

that defines the current TSS A hidden base and limit

register associated with TSS descriptor are loaded

whenever TR is loaded with a new selector Return-

ing from a task is accomplished by the IRET instruc-

tion When IRET is executed control is returned to

the task which was interrupted The currently exe-

cuting task’s state is saved in the TSS and the old

task state is restored from its TSS

Several bits in the flag register and machine status

word (CR0) give information about the state of a

task which is useful to the operating system The

Nested Task bit NT controls the function of the

IRET instruction If NTe0 the IRET instruction per-

forms the regular return If NTe1 IRET performs a

task switch operation back to the previous task The

NT bit is set or reset in the following fashion

When a CALL or INT instruction initiates a task

switch the new TSS will be marked busy and

the back link field of the new TSS set to the old

TSS selector The NT bit of the new task is set

by CALL or INT initiated task switches An in-

terrupt that does not cause a task switch will

clear NT (The NT bit will be restored after exe-

cution of the interrupt handler) NT may also be

set or cleared by POPF or IRET instructions

The Intel386 SX Microprocessor task state segment

is marked busy by changing the descriptor type field

from TYPE 9 to TYPE 0BH An 80286 TSS is

marked busy by changing the descriptor type field

from TYPE 1 to TYPE 3 Use of a selector that refer-

ences a busy task state segment causes an excep-

tion 13

The VM (Virtual Mode) bit is used to indicate if a task

is a Virtual 8086 task If VMe1 then the tasks will

use the Real Mode addressing mechanism The vir-

tual 8086 environment is only entered and exited by

a task switch

The coprocessor’s state is not automatically saved

when a task switch occurs The Task Switched Bit

TS in the CR0 register helps deal with the coproces-

sor’s state in a multi-tasking environment Whenever

the Intel386 SX Microprocessor switches task it

sets the TS bit The Intel386 SX Microprocessor de-

tects the first use of a processor extension instruc-

tion after a task switch and causes the processor

extension not available exception 7 The exception

handler for exception 7 may then decide whether to

save the state of the coprocessor

The T bit in the Intel386 SX Microprocessor TSS

indicates that the processor should generate a de-

bug exception when switching to a task If Te1 then

upon entry to a new task a debug exception 1 will be

generated

32

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