IS25LQ080 データシートの表示（PDF） - Integrated Silicon Solution

部品番号

コンポーネント説明

メーカー

IS25LQ080

8 Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

Integrated Silicon Solution 

DEVICE OPERATION (CONTINUED)

IS25LQ080

FRDIO COMMAND (FAST READ DUAL I/O) OPERATION

The FRDIO instruction is similar to the FRDO

instruction, but allows the address bits to be input two

bits at a time. This may allow for code to be executed

directly from the SPI in some applications.

The FRDIO instruction code is followed by three

address bytes (A23 – A0) and a mode byte,

transmitted via the IO0 and IO1 lines, with each pair of

bits latched-in during the rising edge of SCK. The

address MSb is input on IO1, the next bit on IO0, and

continues to shift in alternating on the two lines. The

mode byte contains the value Ax, where x is a “don’t

care” value. Then the first data byte addressed is

shifted out on the IO1 and IO0 lines, with each pair of

bits shifted out at a maximum frequency fCT, during the

falling edge of SCK. The MSb is output on IO1, while

simultaneously the second bit is output on IO0. Figure

15 illustrates the timing sequence.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDIO instruction. FRDIO

instruction is terminated by driving CE# high (VIH).

The device expects the next operation will be another

FRDIO. It remains in this mode until it receives a

Mode Reset (FFh) command. In subsequent FRDIO

execution, the command code is not input, saving

timing cycles as described in Figure 16. If a FRDIO

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)

CE#

SCK

IO0

012345

67

8 9 10 11 18 19 20 21

...

INSTRUCTION = 1011 1011b

3 - BYTE ADDRESS

22 21 19

... 2 0

MODE BITS

64

IO1

23 22 20

... 3 1 7 5

CE#

22 23 24 25 26 27 28 29 30 31

SCK

IO0

6 42 06 42 06

DATA OUT 1

DATA OUT 2

IO1

753 17 5 317

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

10/18/2012

21

Share Link: