IS42S32400E データシートの表示（PDF） - Integrated Silicon Solution
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IS42S32400E Datasheet PDF : 60 Pages
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IS42S32400E, IS45S32400E
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-6
-7
-75E
Symbol Parameter
Min. Max.
Min. Max.
Min. Max. Units
tck3
Clock Cycle Time
tck2
CAS Latency = 3
CAS Latency = 2
6
—
7
—
——
ns
10 —
10 —
7.5 —
ns
tac3
Access Time From CLK
tac2
CAS Latency = 3
CAS Latency = 2
— 5.4
— 5.4
——
ns
— 6.5
— 6.5
— 5.5
ns
tchi
CLK HIGH Level Width
2.5 —
2.5 —
2.5 —
ns
tcl
CLK LOW Level Width
2.5 —
2.5 —
2.5 —
ns
toh3
Output Data Hold Time
toh2
CAS Latency = 3
CAS Latency = 2
2.7 —
2.7 —
2.7 —
ns
2.7 —
2.7 —
2.7 —
ns
tlz
Output LOW Impedance Time
0
—
0
—
0
—
ns
thz3
thz2
Output HIGH Impedance Time CAS Latency = 3
CAS Latency = 2
2.7 5.4
2.7 5.4
——
ns
2.7 6.5
2.7 6.5
2.7 5.5
ns
tds
Input Data Setup Time(2)
tdh
Input Data Hold Time(2)
tas
Address Setup Time(2)
1.5 —
1.5 —
1.5 —
ns
0.8 —
0.8 —
0.8 —
ns
1.5 —
1.5 —
1.5 —
ns
tah
Address Hold Time(2)
0.8 —
0.8 —
0.8 —
ns
tcks
CKE Setup Time(2)
1.5 —
1.5 —
1.5 —
ns
tckh
CKE Hold Time(2)
0.8 —
0.8 —
0.8 —
ns
tcs
Command Setup Time (CS, RAS, CAS, WE, DQM)(2)
1.5 —
1.5 —
1.5 —
ns
tch
Command Hold Time (CS, RAS, CAS, WE, DQM)(2)
0.8 —
0.8 —
0.8 —
ns
trc
Command Period (REF to REF / ACT to ACT)
60 —
67.5 —
67.5 —
ns
tras
Command Period (ACT to PRE)
42 100K
45 100K
45 100K
ns
trp
Command Period (PRE to ACT)
18 —
20 —
15 —
ns
trcd Active Command To Read / Write Command Delay Time
18 —
20 —
15 —
ns
trrd
Command Period (ACT [0] to ACT[1])
12 —
14 —
15 —
ns
tdpl
Input Data To Precharge
Command Delay time
12 —
14 —
15 —
ns
tdal
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
30 —
35 —
30 —
ns
tmrd Mode Register Program Time
12 —
14 —
15 —
ns
tdde
Power Down Exit Setup Time
6
—
7
—
7.5 —
ns
txsr
Exit Self-Refresh to Active Time (4)
70 —
70 —
70 —
ns
tt
Transition Time
0.3 1.2
0.3 1.2
0.3 1.2
ns
tref
Refresh Cycle Time (4096)
Ta ≤ 70oC Com., Ind., A1, A2
Ta ≤ 85oC Ind., A1, A2
Ta > 85oC A2
— 64
— 64
— 64
ms
— 64
— 64
— 64
ms
— 16
— 16
——
ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tr /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil
(max).
4. Self-Refresh Mode is not supported for A2 grade with Ta > 85oC.
16
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
05/18/09
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