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IS61S6432-117PQ データシートの表示(PDF) - Integrated Silicon Solution
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コンポーネント説明
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IS61S6432-117PQ
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
Integrated Silicon Solution
IS61S6432-117PQ Datasheet PDF : 19 Pages
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IS61S6432
ISSI
®
WRITE CYCLE TIMING
CLK
ADSP
ADSC
ADV
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
t
KC
t
KH
t
KL
t
SS
t
SH
ADV must be inactive for ADSP Write
t
AVS
t
AS
t
AH
WR1
t
WS
WR2
t
WH
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
AVH
WR3
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
WR1
WR2
WR3
t
CES
t
CEH
CE1 Masks ADSP
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
OE
DATA
OUT
High-Z
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
DATA
IN
High-Z
1a
2a
2b
2c
2d
3a
Single Write
Burst Write
Write
Unselected
PB
Integrated Silicon Solution, Inc.
•
1-800-379-4774
Rev.
B
06/28/01
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