ISL12024 データシートの表示（PDF） - Intersil

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ISL12024

Real-Time Clock/Calendar with Embedded Unique ID

Intersil 

ISL12024

AC Electrical Specifications (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

(Note 12) TYP (Note 12) UNITS NOTES

Cpin SDA and SCL Pin Capacitance

10

pF

tWC Non-Volatile Write Cycle Time

tR

SDA and SCL Rise Time

From 30% to 70% of VDD (Note 11)

12

20

ms

20 +

0.1 x Cb

300

ns

11

tF

SDA and SCL Fall Time

From 70% to 30% of VDD (Note 11)

20 +

0.1 x Cb

300

ns

11

Cb Capacitive Loading of SDA or Total on-chip and off-chip. (Note 11)

SCL

10

400

pF

11

RPU SDA and SCL Bus Pull-up

Maximum is determined by tR and tF.

1

Resistor Off-chip

For Cb = 400pF, max is about 2kΩ~2.5kΩ.

For Cb = 40pF, max is about 15kΩ~20kΩ

kΩ

11

NOTES:

3. IRQ/FOUT Inactive.

4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz

5. VDD > VBAT +VBATHYS

6. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V

7. Specified at +25°C.

8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.

9. Parameter is not 100% tested.

10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end

of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.

11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device

specification.

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

Timing Diagrams

Bus Timing

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

Write Cycle Timing

tF

tHIGH

tSU:DAT

tHD:STA

tLOW

tR

tHD:DAT

tAA

tDH

tHD:STO

tSU:STO

tBUF

SCL

SDA

8TH BIT OF LAST BYTE

ACK

5

tWC

STOP

CONDITION

START

CONDITION

FN6370.3

August 18, 2008

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