ISL6209 データシートの表示（PDF） - Intersil
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ISL6209 Datasheet PDF : 10 Pages
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GATE A
DELAY = VCC
GATE B
ISL6209
GATE A
DELAY = RESISTOR TO GROUND
GATE B
tPDHUGATE
1V
tdelay = 5n - 50ns
1V
FIGURE 4. PROGRAMMABLE DEAD-TIME: TOTAL DELAY = tPDHUGATE + tdelay
4
50
45
40
35
30
tDELAY
25
20
15
10
5
0
0
50
100
150
200
250
300
RDELAY (kΩ)
FIGURE 5. ADDITIONAL PROGRAMMED DEAD-TIME
(tDELAY) vs DELAY RESISTOR VALUE
The equation governing the dead-time seen in Figure 5 is
expressed as:
TDELAY = [(160 × 10–15 ) × RDELAY] + 6ns
The equation can be rewritten to solve for RDELAY as
follows:
RDELAY = -(--T----1D---6-E--0--L---×A----Y-1---0-–---–--6-1---n5---s----)
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
CB
O
OT
≥
---Q----G-----A----T---E----
∆VBOOT
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, QGATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.22µF. A
good quality ceramic capacitor is recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
20nC
0.0
QGATE = 100nC
50nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆VBOOT(V)
FIGURE 6. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
7
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