ISL6323 データシートの表示（PDF） - Intersil

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ISL6323

Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

Intersil 

Typical Application - PVI Mode

ISL6323

FB

COMP

ISEN3+

ISEN3-

PWM3

VSEN

BOOT1

UGATE1

PHASE1

APA

LGATE1

ISEN1-

+5V

DVC

ISEN1+

VCC

OFS

FS

PVCC1_2

BOOT2

UGATE2

PHASE2

RSET

LGATE2

VID0

VID1/SEL

VID2

ISEN2-

ISEN2+

VID3

VID4

RGND

VID5

NC PWROK

VDDPWRGD ISEN4+

GND

ISEN4-

+12V

PWM4

ISL6323

OFF

ON

PVCC_NB

EN

BOOT_NB

UGATE_NB

PHASE_NB

LGATE_NB

COMP_NB ISEN_NB-

FB_NB

ISEN_NB+

RGND_NB

+12V

+12V

+12V

VDD

CPU

LOAD

+12V

+12V

BOOT1

UGATE1

PHASE1

LGATE1

PWM1

PGND

ISL6614 +12V

VCC

BOOT2 PVCC

UGATE2GND

PHASE2

PWM2

LGATE2

NORTH BRIDGE REGULATOR

DISABLED IN PVI MODE

VDDNB

NB

LOAD

5

FN9278.2

April 7, 2008

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