TDA1307 データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
メーカー
TDA1307 Datasheet PDF : 36 Pages
| |||
Philips Semiconductors
High-performance bitstream digital filter
Preliminary specification
TDA1307
handbook, full pagewidth
RAB
CL
DA (TDA1307)
DA (µP)
DA
tDWR
tDSP
1
READ PEAK DATA
tDHP
Q1 Q2 Q3
Q31 Q32
Q1 Q2 Q3
Q31 Q32
MGB996
Fig.8 Peak data output protocol.
Multiple format input interface
Data input to the TDA1307 is accepted in four possible
formats, I2S (with word lengths of up to 20 bits), and Sony
formats of word lengths 16, 18 and 20-bit. The general
appearance of the allowed formats is given in Fig.9. The
selection of a format is achieved through programming of
the appropriate bits in the microprocessor register file.
Characteristic timing for the input interface is given in the
diagram of Fig.10.
SYNCHRONIZATION
For correct data input to reach the central controller of
TDA1307, synchronization needs to be achieved to the
incoming 1fs I2S or Sony format input signals.
The incoming WS signal is sampled to detect whether its
phase transitions occur at the correct synchronous timing
instants. This sampling occurs at the TDA1307 internal
clock rate, 256fs. After one phase transition of WS, the
next is expected after a fixed delay, otherwise the
condition is regarded as out-of-lock and a reset is
performed, this operation is repeated until synchronization
is achieved. To allow for slight disturbances causing
unnecessary frequent resets, the critical WS transitions
are expected within a tolerance window (−4 to +4 periods
of the 256fs internal sampling clock instants).
The reset action is flagged on the RESYNC (pin 19)
output, which may be optionally used for muting or related
purposes. RESYNC becomes HIGH the instant a reset is
initiated, and remains in that state for at least one sample
period (1/fs).
ERROR FLAG INPUT EFAB
The error flag input EFAB (pin 4) is intended as request
line from the system decoder to the digital filter to indicate
erroneous audio samples requiring concealment.
A detected HIGH on input EFAB will be relayed by the
input interface block to the error concealment block, where
the samples flagged as erroneous will be processed
accordingly.
1996 Jan 08
13
Share Link: 