K524G2GACB-A050 データシートの表示（PDF） - Samsung

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K524G2GACB-A050

4Gb NAND Flash + 2Gb Mobile DDR

Samsung 

K524G2GACB-A050

Multi-Chip Package MEMORY

4Gb (256M x16) NAND Flash Memory / 2Gb (64M x32) Mobile DDR SDRAM

MCP MEMORY

2. FEATURES

<Common>

• Operating Temperature : -25°C ~ 85°C

• Package : 137-ball FBGA Type - 10.5 x 13 x 1.2mmt, 0.8mm pitch

<NAND Flash>

• Voltage Supply : 1.7V ~ 1.95V

• Organization

- Memory Cell Array :

(256M + 8M) x 16bit for 4Gb

(512M + 16M) x 16bit for 8Gb DDP

- Data Register : (1K + 32) x 16bit

• Automatic Program and Erase

- Page Program : (1K + 32)Word

- Block Erase : (64K + 2K)Word

• Page Read Operation

- Page Size : (1K + 32)Word

- Random Read : 40µs(Max.)

- Serial Access : 42ns(Min.)

• Fast Write Cycle Time

- Page Program time : 250µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

-Endurance : 100K Program/Erase Cycles

with 1bit/256Word ECC for x16

• Command Driven Operation

• Unique ID for Copyright Protection

<Mobile DDR>

• VDD/VDDQ = 1.8V/1.8V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• MRS cycle with address key programs

- CAS Latency ( 3 )

- Burst Length ( 2, 4, 8, 16 )

- Burst Type (Sequential & Interleave)

• EMRS cycle with address key programs

- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )

- Output Driver Strength Control

( Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8 )

• Internal Temperature Compensated Self Refresh

• All inputs except data & DM are sampled at the positive going edge of

the system clock(CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• DM0 - DM3 for write masking only.

• Auto refresh duty cycle

- 7.8us

• Clock stop capability

Operating Frequency

Speed @CL31)

Note:

1) CAS Latency

DDR333

166MHz

DDR400

200MHz

Address configuration

Organization

64Mx32

Bank

BA0,BA1

Row

A0 - A13

- DM is internally loaded to match DQ and DQS identically.

Column

A0 - A9

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

-3-

Revision 1.3

November 2009

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