MU9C8358 データシートの表示（PDF） - Music Semiconductors

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MU9C8358

Quad 10/100Mb Ethernet Filter Interface

Music Semiconductors 

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MU9C8358 internal functions are shown in Figure 4.

Before discussing the individual blocks, the underlying

principals are presented. The network interfaces are

monitored for network and data symbol errors. Receive

data [RXD] is clocked into a register using the 25MHz

recovered clock for 100Base-X or 2.5MHz clock for

10Base-X. The Preamble and Start Frame delimiter (SFD)

are scanned to locate the Destination address (DA) and the

Source address (SA).

An addressing mechanism uniquely identifies each

MU9C8358 in a system. The Master MU9C8358

schedules communication with the host processor and the

CAM through an arbitration process. Once the system is

initialized and configured, highest-priority is given to

network traffic.

The LANCTL block generates the command cycles and

operational codes to complete CPU-requested actions and

network-generated requests. The CPU must initialize the

CAM, write the permanent station list, and initiate other

housekeeping functions. Network traffic initiates DA

filtering, SA learning, and time stamp updates. All

state-machines required for real-time operations are

implemented in the ASIC hardware; the host CPU runs the

non-time-critical initialization routine.

Information on the LANCAM operation and instruction

set can be found in the appropriate LANCAM data sheet

for each device.

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Figure 4: MU9C8358 Functional Block Diagram



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