KSZ8842-PMQL データシートの表示（PDF） - Micrel
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KSZ8842-PMQL Datasheet PDF : 119 Pages
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Micrel, Inc.
KSZ8842-PMQL/PMBL
Pin
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pin
Name
NC
AGND
VDDA
NC
RXP1
RXM1
AGND
TXP1
TXM1
VDDATX
VDDARX
RXM2
RXP2
AGND
TXM2
TXP2
VDDA
AGND
NC
NC
ISET
AGND
VDDAP
AGND
X1
X2
67
RSTN
68
PAR
69
FRAMEN
70
IRDYN
Type
Pin Function
—
No connect
Gnd Analog ground
P
1.2V analog VDD
—
No connect
I/O
Physical receive (MDI) or transmit (MDIX)signal (+ differential)
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential)
Gnd Analog ground
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential)
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential)
P
3.3V analog VDD
P
3.3V analog VDD
I/O
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
I/O
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
Gnd Analog ground
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
P
1.2 analog VDD
Gnd Analog ground
—
No connect
—
No connect
O
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
Gnd Analog ground
P
1.2V analog VDD for PLL
Gnd Analog ground
I
25MHz crystal/oscillator clock connections
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is not connected.
Note: Clock is ±50ppm for both crystal and oscillator.
Ipu Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMQL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
I/O
PCI Parity
Even parity computed for PAD [31:0] and CBE [3:0]N, master drives PAR for address
and write data phase, target drives PAR for read data phase.
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction in a bus master mode. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed to it.
I/O
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]
during write data phases, indicates it is ready to accept data during read data phases.
As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on
the bus.
October 2007
13
M9999-100207-1.5
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