KSZ8842-PMQL データシートの表示（PDF） - Micrel

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KSZ8842-PMQL

2-Port Ethernet Switch with PCI Interface

Micrel 

Micrel, Inc.

KSZ8842-PMQL/PMBL

Ball

Number

Ball

Name

Type

B4

INTRN

Opd

A4

EECS

Opu

C3

P2LED3 Opd

A3

EEEN

Ipd

B3

P1LED3 Opd

B2

EEDO

Opd

A2

EESK

Opd

A1

EEDI

Ipd

B1

PWRDN Ipu

C1

RXP1

I/O

C2

RXM1

I/O

D1

TXP1

I/O

D2

TXM1

I/O

F2

RXM2

I/O

F1

RXP2

I/O

G2

TXM2

I/O

G1

TXP2

I/O

G3

ISET

O

H1

X1

I

H2

X2

O

J1

RSTN

Ipu

J2

PAR

O

K1

FRAMEN I/O

Ball Function

defines the start of each phase. The clock maximum frequency is 33MHz.

Interrupt Request. Active Low signal to host CPU to request an interrupt when any one of the

interrupt conditions occurs in the registers. This pin should be pull-up externally.

EEPROM Chip Select. This signal is used to select an external EEPROM device

Port 2 LED Indicator

See the description in ball B5, B6 and A6.

EEPROM Enable

EEPROM is enabled and connected when this pin is pull-up.

EEPROM is disabled when this pin is pull-down or no connect.

Port 1 LED indicator

See the description in ball C7, A7 and B7.

EEPROM Data Out:

This pin is connected to DI input of the serial EEPROM.

EEPROM Serial Clock:

A 4µs serial output clock to load configuration data from the serial EEPROM.

EEPROM Data In:

This pin is connected to DO output of the serial EEPROM.

Full-chip power-down. Active Low.

Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)

Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)

Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)

Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)

Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)

Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)

Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)

Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)

Set physical transmit output current.

Pull-down this ball with a 3.01K 1% resistor.

25MHz crystal/oscillator clock connections

Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant

oscillator and X2 is a no connect.

Note: Clock is ± 50ppm for both crystal and oscillator.

Hardware Reset, Active Low

RSTN will cause the KSZ8842-PMBL to reset all of its functional blocks. RSTN must be

asserted for a minimum duration of 10 ms.

PCI Parity

Even parity computed for PAD [31:0] and CBE[3:0]N, master drives PAR for address and

write data phase, target drives PAR for read data phase.

PCI Cycle Frame

This signal is asserted low to indicate the beginning of the address phase of the bus

transaction and de-asserted before the final transfer of the data phase of the transaction in a

bus master mode. As a target, the device monitors this signal before decoding the address to

check if the current transaction is addressed to it.

October 2007

17

M9999-100207-1.5

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