KSZ8993M データシートの表示（PDF） - Micrel

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KSZ8993M

Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel 

Micrel, Inc.

KSZ8993M/ML

Pin Number

100

101

Pin Name

PS1

PS0

Type (1)

Ipd

Ipd

102

PV31

Ipu

103

PV32

Ipu

Note:

1. I = Input.

O= Output.

Ipu = Input w/ internal pull-up.

Ipd = Input w/ internal pull-down.

Description

Serial bus configuration pins to select mode of access to

KSZ8993M internal registers.

[PS1, PS0] = [0, 0] — I2C master (EEPROM) mode

(If EEPROM is not detected, the power-up default values of

the KSZ8993M internal registers will be used.)

Interface Signals

SPIQ

SCL

SDA

SPIS_N

Type

O

O

I/O

Ipu

Description

Not used (tri-stated)

I2C clock

I2C data I/O

Not used

[PS1, PS0] = [0, 1] — I2C slave mode

The external I2C master will drive the SCL clock.

The KSZ8993M device addresses are:

1011_1111 <read>

1011_1110 <write>

Interface Signals Type Description

SPIQ

SCL

SDA

O

Not used (tri-stated)

I

I2C clock

I/O

I2C data I/O

SPIS_N

Ipu Not used

[PS1, PS0] = [1, 0] — SPI slave mode

Interface Signals Type Description

SPIQ

O

SPI data out

SCL

I

SPI clock

SDA

I

SPI data In

SPIS_N

Ipu SPI chip select

[PS1, PS0] = [1, 1] – SMI-mode

In this mode, the KSZ8993M provides access to all its internal

8 bit registers through its MDC and MDIO pins.

Note:

When (PS1, PS0) ≠ (1,1), the KSZ8993M provides access to

its 16 bit MIIM registers through its MDC and MDIO pins.

Port 3 port-based VLAN mask bits – Use to select which

ports may transmit packets received on port 3.

PV31 = 1, port 1 may transmit packets received on port 3

PV31 = 0, port 1 will not transmit any packets received on

port 3

PV32 = 1, port 2 may transmit packets received on port 3

PV32 = 0, port 2 will not transmit any packets received on

port 3

I/O = Bi-directional.

October 2008

16

M9999-020606

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