DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

KS8995M(2003) データシートの表示(PDF) - Micrel

部品番号
コンポーネント説明
メーカー
KS8995M
(Rev.:2003)
Micrel
Micrel Micrel
KS8995M Datasheet PDF : 73 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
KS8995M
Micrel
Pin Number
59
60
61
62
63
64
65
Pin Name
VDDIO
PMRXC
PMRXDV
PMRXD3
PMRXD2
PMRXD1
PMRXD0
66
PMRXER
67
PCRS
68
PCOL
69
SMTXEN
70
SMTXD3
71
SMTXD2
72
SMTXD1
73
SMTXD0
74
SMTXER
75
SMTXC
76
GNDD
77
VDDIO
78
SMRXC
79
SMRXDV
80
SMRXD3
81
SMRXD2
Type(1)
P
O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
Gnd
P
I/O
Ipd/O
Ipd/O
Ipd/O
Port
5
5
5
5
5
5
5
5
5
Pin Function
3.3/2.5V digital VDD for digital I/O circuitry
PHY[5] MII receive clock. PHY mode MII
PHY[5] MII receive data valid
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
PHY[5] MII carrier sense/Force duplex mode. See Register 76for
port 4 only. PD (default) = Force half-duplex if auto-negotiation is
disabled or fails. PU = Force full-duplex if auto-negotiation is disabled
or fails.
PHY[5] MII collision detect/ Force flow control. See Register 66for
port 4 only. PD (default) = No force flow control. PU = Force flow
control.
Switch MII transmit enable
Switch MII transmit bit 3
Switch MII transmit bit 2
Switch MII transmit bit 1
Switch MII transmit bit 0
Switch MII transmit error
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
Digital ground
3.3/2.5V digital VDD for digital I/O circuitry
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
Switch MII receive data valid
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
December 2003
11
M9999-120403

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]