KSZ8995FQ データシートの表示（PDF） - Micrel

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KSZ8995FQ

Integrated 5-Port 10/100 Managed Switch

Micrel 

Micrel, Inc.

KS8995MA/FQ

List of Figures

Figure 1. Broadband Gateway ............................................................................................................................................ 11

Figure 2. Integrated Broadband Router .............................................................................................................................. 11

Figure 3. Standalone Switch ............................................................................................................................................... 12

Figure 4. Using KS8995FQ for Dual Media Converter or Fiber Daisy Chain Connection .................................................. 12

Figure 5. Auto Negotiation .................................................................................................................................................. 28

Figure 6. DA Look-Up Flowchart − 1................................................................................................................................... 31

Figure 7. DA Resolution Flowchart − Stage 2 ..................................................................................................................... 32

Figure 8. KS8995MA/FQ EEPROM Configuration Timing Diagram ................................................................................... 43

Figure 9. SPI Write Data Cycle ........................................................................................................................................... 44

Figure 10. SPI Read Data Cycle ........................................................................................................................................... 44

Figure 11. SPI Multiple Write ................................................................................................................................................ 45

Figure 12. SPI Multiple Read ................................................................................................................................................ 45

Figure 13. EEPROM Interface Input Receive Timing Diagram............................................................................................. 79

Figure 14. EEPROM Interface Output Transmit Timing Diagram......................................................................................... 79

Figure 15. SNI Input Timing .................................................................................................................................................. 80

Figure 16. SNI Output Timing ............................................................................................................................................... 80

Figure 17. MAC Mode MII Timing − Data Received from MII ............................................................................................... 81

Figure 18. MAC Mode MII Timing − Data Transmitted from MII ........................................................................................... 81

Figure 19. PHY Mode MII Timing − Data Received from MII................................................................................................ 82

Figure 20. PHY Mode MII Timing − Data Transmitted from MII............................................................................................ 82

Figure 21. SPI Input Timing .................................................................................................................................................. 83

Figure 22. SPI Output Timing................................................................................................................................................ 84

Figure 23. Reset Timing ........................................................................................................................................................ 85

Figure 24. Recommended Reset Circuit ............................................................................................................................... 86

Figure 25. Recommended Circuit for Interfacing with CPU/FPGA Reset............................................................................. 86

October 2011

9

M9999-102611-3.0

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