Philips Semiconductors
Terrestrial Digital Sound Decoder (TDSD3)
Preliminary specification
SAA7283
OVW
This bit is set when new additional data bits are written to
the I2C-bus without the previous bits being read.
SAD
This bit is set HIGH when new additional data is written
into the I2C-bus, and cleared by the action of reading the
data.
CI1 AND CI2
These are the CI bits decoded by majority logic from the
parity checks of the last ten samples in a frame.
AD10, AD9 AND AD8
These are the three most significant additional data bits.
C1, C2 AND C3
These are the transmitted control bits, see Table 13.
BG/I
When set HIGH this bit indicates that the DQPSK
demodulator is switched to system BGH. When LOW,
indicates that DQPSK demodulator is switched to
system I.
Indicator bits
Table 13 is the truth table for the indicator bits.
Table 13 Indicator bits functional truth table
TRANSMISSION
C1
C2
Stereo
0
0
M1 + M2
0
1
M1 + data
1
0
Transparent data
1
1
Any currently undefined combination of C1, C2 and C3
Decoder unsynchronized (OS = logic 0)
C3
S/M
D/S
VDSP
OS
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1996 Oct 24
17