L6910 データシートの表示（PDF） - STMicroelectronics
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L6910 Datasheet PDF : 29 Pages
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L6910 - L6910A
9 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY
Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact
that the trace between the driving chipset and the memory input must be terminated with resistors.
Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable
of sourcing and sinking current.
Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is
a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is
2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination
voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x
L6910. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage.
The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through
a resistor divider connected to the 2.5V.
Figure 23. Application idea : DDR Memory Supply
VIN
12V
BOOT
OCSET
12
VCC
15
3
UGATE
11
GND
7
U1
PHASE
10
LGATE
14
SS
STS11NF3LL
4 L6910 13 PGND
OSC
2
9 PGOOD
EAREF
8
5
VREF
1
6
STS11NF3LL
VDDQ
2.5V@15A
DDR
MEMORY
PWRGD
TERMINATION
NETWORK
VREF
VIN
12V
R
R
BOOT
OCSET
VCC 12
15
3
UGATE
11
GND
7
U2
PHASE
10
14 LGATE
SS
4 L6910 13 PGND
OSC
2
9 PGOOD
EAREF
8
5
VREF
1
6
STS8DNF3LL
VTT
1.25V@ +- 5A
PWRGD
CHIPSET
-
+
The current required by the memory and the termination supply, depends on the memory type and size.
The figure 24, 25 shows the efficiency of the L6910 for the termination section of the application shown in fig.
23, in sink and source mode. The figures show the efficiency values also when the input voltage is coming di-
rectly from the 12V rail.
20/29
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