LC7153 データシートの表示（PDF） - SANYO -> Panasonic

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LC7153

Universal Dual-PLL Frequency Synthesizers

SANYO -> Panasonic 

LC7153, 7153M

Mode 2 command format and functions

The Mode 2 command comprises the data bits which de-

termine the reference frequency divider ratio and control

functions. The command format is shown in figure 3. Bit

R0 is the first bit received.

Figure 3. Mode 2 command (reference divider and control data)

Bits R0 to R13 determine the reference divider ratio. The

range of allowable divider ratios is NR=8 (0008H) to 16383

(3FFFH).

Bits FL0 and FL1 are the fast lock-up mode select bits.

The fast lock-up modes are shown in table 2. The higher

the mode number, the greater the expansion width of the

detected phase error signal.

FL0 FL1

Fast lock-up mode

0

0

0

1

0

1

0

1

2

1

1

3

Bits OA and OB are the uncommitted output control bits.

They are latched and then inverted to control OUTA and

OUTB, respectively. If either bit is 1, the open-drain out-

put is pulled LOW.

Figure 4. Fast lock-up operating modes

Bit SB is the standby mode control bit. When SB=1, standby

mode is selected. In standby mode, PLLB is stopped, PIB

is pulled LOW, and PDB1 and PDB2 are high impedance.

When SB=0, normal operation is selected.

Bits FA and FB are the input frequency range select bits.

The PIA and PIB frequency ranges, set by FA and FB, re-

spectively, are shown in table 3.

Table 3. Frequency ranges

FA, FB Input frequency range Unit

0

1.5 to 40.0

MHz

1

35 to 160

MHz

Bits HSA, HSB and HSM are the fast lock-up control bits.

When HSA or HSB=1, the fast lock-up circuits for PLLA

or PLLB, respectively, are ON. When HSA or HSB=0, the

respective circuits are OFF. For use with FM, the fast lock-

up circuits should be OFF. HSM determines the fast lock-

up operating mode. When HSM=0, operating mode 0 is

selected and the fast lock-up only operates when the PLLs

are unlocked. When HSM=1, operating mode 1 is selected

and the fast lock-up operates normally, as shown in figure

4.

Bits UL0 and UL1 determine the unlock detection thresh-

old. The PLL unlock detector output, LDA or LDB, is pulled

LOW when the phase differential between the reference

and the divider inputs exceeds the threshold set by UL0

and UL1. The threshold for different crystal frequencies is

shown in table 4, and the threshold for other frequencies

can be calculated. The threshold is common to both PLLs.

Note that a PLL will temporarity lose lock when either UL0

or UL1 is changed.

No.4160–7/11

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