LC72131KM データシートの表示（PDF） - SANYO -> Panasonic

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LC72131KM

CMOS IC PLL Frequency Synthesizer

SANYO -> Panasonic 

LC72131K, 72131KM

Continued from preceding page.

No.

Control block/data

(8) Phase comparator

control data

DZ0, DZ1

Functions

• Controls the phase comparator dead zone.

DZ1 DZ0

0

0

0

1

1

0

1

1

Dead zone mode

DZA

DZB

DZC

DZD

Dead zone width: DZA<DZB<DZC<DZD

(9) Clock time base

Setting TBC to one causes an 8Hz, 40% duty clock time base signal to be output from the BO1

TBC

pin. (BO1 data is invalid in this mode.)

(10) Charge pump control Forcibly controls the charge pump output.

data

DLC

Charge pump output

DLC

0

Normal operation

1

Forced low

(11) IF counter control

data

IFS

(12) LSI test data

TEST0 to 2

(13) DNC

Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO

oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and

setting Vtune to VCC. (This is the deadlock clearing circuit.)

This data must be set 1 in normal mode.

IFS Though if this value is set to zero, the system enters input sensitivity degradation mode,

and the sensitivity is reduced to 10 to 30mVrms.

* See the “IF Counter Operation” item for details.

LSI test data

TEST0

TEST1 These values must all be set to 0.

TEST2

These test data are set to 0 automatically after the power-on reset.

Don’t care. This data must be set to 0.

Related data

BO1

DO Control Data (Serial Data Output) Structure

[3] OUT Mode

address

DI

01010100

Fist Data OUT

DO

Ì: Must be 0.

No.A0788-11/22

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