LC7861KE データシートの表示（PDF） - SANYO -> Panasonic

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LC7861KE

Digital Signal Processor for Compact Disc Players

SANYO -> Panasonic 

LC7861KE

13. Reset circuit; Pin 55: RES

When power is first applied, this pin should be briefly set low and then set high. This will set the muting to –∞ dB

and stop the disk motor.

Constant linear velocity servo

START

STOP

BRAKE

CLV

Muting control

0 dB

–12 dB

∞

Q subcode address conditions

Address 1

Address free

Laser control

ON (low)

OFF

(high)

Track jump mode

Standard

New

Track count mode

Standard

New

14. De-emphasis ON/OFF; Pin 29: EMPH

The preemphasis on/off bit in subcode Q control information is output from the EMPH pin. De-emphasis should be

performed when this signal is high.

15. Error flag output; Pin 45: EFLG, pin 49: FSX

The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.

The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined

from the extent of the high level that appears here.

16. Crystal clock oscillator; Pin 63: XIN, pin 64: XOUT

MSB

LSB

10001110

10001101

11000001

11000010

01100000

01100001

Command

OSC ON

OSC OFF

DOUBLE SPEED MODE

NORMAL MODE

VCO 8M

VCO 16M

RES = low

o

o

o

No. 4818-14/18

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