LFECP10E-5T144I データシートの表示（PDF） - Lattice Semiconductor
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LFECP10E-5T144I Datasheet PDF : 163 Pages
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Lattice Semiconductor
Revision History
LatticeECP/EC Family Data Sheet
Date
Version
September 2005 02.0
November 2005 02.1
March 2006
02.2
January 2007 02.3
February 2007 02.4
May 2007
02.5
November 2007 02.6
February 2008 02.7
Section
Architecture
DC & Switching
Characteristics
Pinout Information
DC & Switching
Characteristics
Ordering Information
DC & Switching
Characteristics
Architecture
Architecture
Architecture
DC & Switching
Characteristics
Pinout Information
Supplemental
Information
DC & Switching
Characteristics
Change Summary
sysIO section has been updated.
Recommended Operating Conditions has been updated with VCCPLL.
DC Electrical Characteristics table has been updated
Removed 5V Tolerant Input Buffer section.
Register-to-Register performance table has been updated (rev. G 0.28).
LatticeECP/EC External Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Internal Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28).
sysCLOCK PLL timing table has been updated (rev. G 0.28)
LatticeECP/EC sysCONFIG Port Timing specification table has been
updated (rev. G 0.28).
Master Clock table has been updated (rev. G 0.28).
JTAG Port Timing specification table has been updated (rev. G 0.28).
Signal Description table has been updated with VCCPLL.
Pin-to-Pin Performance table has been updated (G 0.30)
- 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX
Register-to-Register Performance (G 0.30) - No timing number
changes.
External Switching Characteristics (G 0.30) - No timing number
changes.
Internal Switching Characteristics (G 0.30)
-tSUP_DSP, tHP_DSP, tSUO_DSP, tHO_DSP, tCOI_DSP, tCOD_DSP numbers
have been updated.
Family Timing Adders (G 0.30) - No timing number changes.
sysCLOCK PLL Timing (G 0.30) - No timing number changes.
sysCONFIG Port Timing Specifications (G 0.30) - No timing number
changes.
Master Clock (G 0.30) - No timing number changes.
JTAG Port Timing Specification (G 0.30) - No timing number changes.
Added 208-PQFP lead-free part numbers.
Added footnote 3. to VCCAUX in the Recommended Operating Condi-
tions table.
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated Maximum Number of Elements in a Block table - MAC value
for x9 changed to 2.
Updated text in Ripple Mode section.
Added JTAG Port Waveforms diagram.
Updated tRST timing information in the sysCLOCK PLL Timing table.
Added Thermal Management text section.
Updated title list.
Read/Write Mode (Normal) and Read/Write Mode with Input and Output
Registers waveforms in the EBR Memory Timing Diagrams section
have been updated.
7-3
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