LFECP10E-5F484C データシートの表示（PDF） - Lattice Semiconductor

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LFECP10E-5F484C

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

MULTADDSUM sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/

subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction

are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows

the MULTADDSUM sysDSP element.

Figure 2-22. MULTADDSUM

Shift Register B In

Shift Register A In

Multiplicand A0

Multiplier B0

Multiplicand A1

Multiplier B1

Multiplicand A2

Multiplier B2

Multiplicand A3

Multiplier B3

Signed

Addn0

Addn1

m

m

n

n

n

Input Data

Register B

n

m

Input Data m

Register A

n

m

m

n

n

Input Data

Register B

m

Input Data n

Register A

n

m

m

n

n

n

Input Data

Register B

n

m

Input Data m

Register A

n

m

m

n

n

m

Input Data m

Register A

Input Data

Register B

n

Input

Register

n

m

Pipeline

Register

Input

Register

Pipeline

Register

Input

Register

Pipeline

Register

Multiplier m+n

x

(default)

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Pipeline

Register

Add/Sub0

m+n

(default)

Multiplier

x

Pipeline

Register

m+n+1

SUM

m+n+2

Multiplier m+n

x

(default)

m+n+1

Pipeline

Register

Add/Sub1

m+n

(default)

Multiplier

x

Pipeline

Register

To Add/Sub0, Add/Sub1

To Add/Sub0

To Add/Sub1

Shift Register B Out

Shift Register A Out

Output

m+n+2

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset

and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)

one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and

Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)

at each input register, pipeline register and output register.

2-18

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