LH28F800SG-L データシートの表示（PDF） - Sharp Electronics

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LH28F800SG-L

8 M-bit (512 kB x 16) SmartVoltage Flash Memories

Sharp Electronics 

4.1 Read Array Command

Upon initial device power-up and after exit from

deep power-down mode, the device defaults to

read array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is written. Once the internal WSM has started a

block erase, word write or lock-bit configuration, the

device will not recognize the Read Array command

until the WSM completes its operation unless the

WSM is suspended via an Erase Suspend or Word

Write Suspend command. The Read Array

command functions independently of the VPP

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command write, read cycles from addresses shown

in Fig. 2 retrieve the manufacture, device, block

lock configuration and permanent lock configuration

codes (see Table 4 for identifier code values). To

terminate the operation, write another valid

command. Like the Read Array command, the

Read Identifier Codes command functions

independently of the VPP voltage and RP# can be

VIH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

CODE

ADDRESS DATA

Manufacture Code

00000H 00B0H

Device Code

00001H 0050H

Block Lock Configuration (NOTE 2) XX002H (NOTE 1)

• Unlocked

DQ0 = 0

• Locked

DQ0 = 1

• Reserved for future enhancement

DQ1-15

Permanent Lock Configuration (NOTE 2) 00003H

• Unlocked

DQ0 = 0

• Locked

DQ0 = 1

• Reserved for future enhancement

DQ1-15

NOTES :

1. X selects the specific block lock configuration code to be

read. See Fig. 2 for the device identifier code memory map.

2. Block lock status and permanent lock status are output

by DQ0. DQ1-DQ15 are reserved for future enhancement.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

4.3 Read Status Register Command

The status register may be read to determine when

a block erase, word write, or lock-bit configuration is

complete and whether the operation completed

successfully. It may be read at any time by writing

the Read Status Register command. After writing

this command, all subsequent read operations

output data from the status register until another

valid command is written. The status register

contents are latched on the falling edge of OE# or

CE#, whichever occurs. OE# or CE# must toggle to

VIH before further reads to update the status

register latch. The Read Status Register command

functions independently of the VPP voltage. RP#

can be VIH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are

set to "1"s by the WSM and can only be reset by

the Clear Status Register command. These bits

indicate various failure conditions (see Table 6). By

allowing system software to reset these bits,

several operations (such as cumulatively erasing or

locking multiple blocks or writing several words in

sequence) may be performed. The status register

may be polled to determine if an error occurred

during the sequence.

To clear the status register, the Clear Status

Register command (50H) is written. It functions

independently of the applied VPP voltage. RP# can

be VIH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated

by a two-cycle command. A block erase setup is

first written, followed by a block erase confirm.

This command sequence requires appropriate

sequencing and an address within the block to be

erased (erase changes all block data to FFH).

Block preconditioning, erase, and verify are handled

internally by the WSM (invisible to the system).

After the two-cycle block erase sequence is written,

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