LH521028 データシートの表示（PDF） - Sharp Electronics

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LH521028

CMOS 64K × 18 Static RAM

Sharp Electronics 

LH521028

CMOS 64K × 18 Static RAM

BYTE OPERATIONS (cont’d)

Byte Write Description (Figure 13)

To do individual byte-write operations, the device must

be enabled (E is LOW, G is don’t care) and addresses

must be either stable or latched. Figure 13 is one example

of the byte-write capabilities of this device. The diagram

shows two write operations with unlatched addresses.

The first is a write to the low byte of memory location N

and the second is a write to the high byte of memory

location M.

(1) W goes LOW while SL and SH remain HIGH.

(2) SL goes LOW initiating a Write into the lower byte

DQL(0-8) of memory location N. SH remains HIGH

preventing a Write into the upper byte DQL(9-17) of

memory location N.

(3) SL now goes HIGH terminating the Write operation

on the lower byte of memory location N.

(4) Address N is changed to M.

(5) The Write operationis now initiated on the upper byte

DQH(9-17) by bringing SH LOW. SL remains HIGH

preventing a Write operation from occurring in the

lower byte DQL(0-8) of memory location N+ 1.

(6) SH now goes HIGH terminating the Write operation

on the upper byte of address M.

(7) W goes HIGH, ending the Write operation.

ADDRESS

ALE

W

SL

VALID ADDRESS N

VALID ADDRESS M

SH

DQL (0-8)

DQH (9-17)

(1) (2)

DATA IN (N)

DATA IN (M)

(3) (4)(5)

(6) (7)

Figure 13. Byte Write (E is LOW)

521028-11

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