CMOS 64K × 18 Static RAM
LH521028
TIMING DIAGRAMS – READ CYCLE (cont’d)
Read Cycle No. 3 (Latched Address Controlled
Read)
Chip is in Read Mode: W is HIGH, E, SH, SL and G are
LOW. Both tAA and tLEA must be met before valid data is
available. If the address is valid prior to the rising edge of
ALE, then the access time is tLEA. If the address is valid
after ALE is HIGH (or if ALE is tied HIGH) then the access
time is tAA. Crosshatched portion of Data Out implies that
data lines are in the Low-Z state but the data is not
guaranteed to be valid until tAA.
E, SH, SL
ALE
ADDRESS
DQ
tLHM
tASL
tAHL
VALID ADDRESS
tAA
PREVIOUS DATA
tLEA
tLH
VALID DATA
Figure 6. Read Cycle No. 3
521028-4
4-219