SA8025A データシートの表示（PDF） - Philips Electronics

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SA8025A

Low-voltage 1.8GHz fractional-N synthesizer

Philips Electronics 

Philips Semiconductors

1.8GHz low-voltage Fractional-N synthesizer

Product specification

SA8025A

ǒ Ǔ |IPHI_comp| +

FRD @ IRN

128

(2CL)1) CK

Figure 9 shows that for proper fractional compensation, the area of

the fractional compensation current pulse must be equal to the area

of the charge pump ripple output. This means that the current

setting on the input RN, RF is approximately:

IRN

IRF

[

(Q @ fVCO)

(3 @ CN @ FINR)

where:

Q=

fVCO = fINM × N,

FINR =

fractional-N modulus

input frequency of the prescaler

input frequency of the reference divider

PHI pump is meant for switching only. Current and compensation

are not as accurate as PHP.

Lock Detect

The output LOCK is H when the auxiliary phase detector AND the

main phase detector indicates a lock condition. The lock condition

is defined as a phase difference of less than +1 cycle on the

reference input REF_IN. The lock condition is also fulfilled when the

relative counter is disabled (EM = “0” or respectively EA = “0”) for

the main, respectively auxiliary counter.

Test Modes

The lock output is selectable as fREF, fAUX, fMAIN and lock. Bits T1

and T0 of the E word control the selection (see Figures 6 and 10).

If T1 = T0 = Low, or if the E-word is not sent, the lock output is

configured as the normal lock output described in the Lock Detect

section.

If T1 = Low and T0 = High, the lock output is configured as fREF.

The signal is the buffered output of the reference divider NR and the

3-bit binary counter SM. The fREF signal appears as normally low

and pulses high whenever the divider reaches terminal count from

the value programmed into the NR and SM registers. The fREF

signal can be used to verify the divide ratio of the Reference divider.

If T1 = High and T0 = Low, the lock output is configured as fAUX.

The signal is normally high and pulses low whenever the divider

reaches terminal count from the value programmed into the NA and

PA registers. The fAUX signal can be used to verify the divide ratio

of the Auxiliary divider.

If T1 = High and T0 = High, the lock output is configured as fMAIN.

The signal is the buffered output of the MAIN divider. The fMAIN

signal appears as normally high and pulses low whenever the

divider reaches terminal count from the value programmed into the

NM1, NM2, NM3 or NM4 registers. The fMAIN signal can be used to

verify the divide ratio of the MAIN divider and the prescaler.

Test Pin

The Test pin, Pin 19, is a buffered logic input which is exclusively

ORed with the output of the prescaler. The output of the XOR gate

is the input to the MAIN divider. The Test pin must be connected to

VDD during normal operation as a synthesizer. This pin can be used

as an input for verifying the divide ratio of the MAIN divider; while in

this condition the input to the prescaler, RFIN, may be connected to

VCCP through a 10kΩ resistor in order to place prescaler output into

a known state.

MAIN

DIVIDER

REF

DIVIDER

SM

AUX

DIVIDER

φMAIN

φAUX

T1

T0

SELECT

LOGIC

LOCK

Figure 10. Test Mode Diagram

SR00561

1996 Oct 15

15

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