LRS1383 データシートの表示（PDF） - Sharp Electronics

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LRS1383

Stacked Chip 32M Flash and 8M SRAM

Sharp Electronics 

LRS1383

10

5.2 Identifier Codes and OTP Address for Read Operation

Code

Address

[A15-A0](1)

Data

[DQ15-DQ0]

Notes

Manufacturer Code

Manufacturer Code

0000H

00B0H

Device Code

32M Bottom Parameter Device Code

0001H

00B5H

2

Block is Unlocked

Block is Locked

Block Lock Configuration Code

Block is not Locked-Down

Block is Locked-Down

Device Configuration Code

Partition Configuration Register

Block

Address

+2

0006H

DQ0 = 0

3

DQ0 = 1

3

DQ1 = 0

3

DQ1 = 1

3

PCRC

4

OTP Lock

OTP

OTP

0080H

OTP-LK

5

0081-0088H

OTP

6

Notes:

1. The address A20-A16 to read the manufacturer, device, lock configuration, device configuration code and OTP data are

shown in below table.

2. Bottom parameter device has its parameter blocks in the plane 0 (The lowest address).

3. DQ15-DQ2 is reserved for future implementation.

4. PCRC=Partition Configuration Register Code.

5. OTP-LK=OTP Block Lock configuration.

6. OTP=OTP Block data.

5.3 Identifier Codes and OTP Address for Read Operation on Partition Configuration(1)

Partition Configuration Register

Address (32M-bit device)

PCR.10

PCR.9

PCR.8

[A20-A16]

0

0

0

00H

0

0

1

00H or 08H

0

1

0

00H or 10H

1

0

0

00H or 18H

0

1

1

00H or 08H or 10H

1

1

0

00H or 10H or 18H

1

0

1

00H or 08H or 18H

1

1

1

00H or 08H or 10H or 18H

Notes:

1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read

Identifier Codes/OTP command (90H).

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