LT1952EGN(RevD) データシートの表示（PDF） - Linear Technology

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LT1952EGN
(Rev.:RevD)

Single Switch Synchronous Forward Controller

Linear Technology 

LT1952/LT1952-1

APPLICATIONS INFORMATION

Blanking is provided in 2 phases (Figure 6): The first phase

automatically blanks during gate rise time. Gate rise times

can vary depending on MOSFET type. For this reason the

LT1952/LT1952-1 perform true ‘leading edge blanking’ by

automatically blanking OC and ISENSE comparator outputs

until OUT rises to within 0.5V of VIN or reaches its clamp

level of 13V. The second phase of blanking starts after

the leading edge of OUT has been completed. This phase

is programmable by the user with a resistor connected

from the BLANK pin to ground. Typical durations for this

portion of the blanking period are from 45ns at RBLANK

= 10k to 540ns at RBLANK = 120k. Blanking duration can

be approximated as:

Blanking (extended) = [45(RBLANK/10k)]ns

(see graph in Typical Performance Characteristics)

(AUTOMATIC)

LEADING

EDGE

BLANKING

(PROGRAMMABLE)

EXTENDED

BLANKING

CURRENT

SENSE

DELAY

OUT

RBLANK

(MIN)

= 10k

10k < RBLANK b 240k

100ns

BLANKING

0 Xns X + 45ns

[X + 45(RBLANK/10k)]ns

1952 F06

Figure 6. Leading Edge Blank Timing

Programming Current Limit (OC Pin)

The LT1952/LT1952-1 use a precise 107mV sense threshold

at the OC pin to detect overcurrent conditions in the

converter and set a soft-start latch. It is independent of

duty cycle because it is not affected by slope compensation

programmed at the ISENSE pin. The OC pin monitors the

peak current in the primary MOSFET by sensing the

voltage across a sense resistor (RS) in the source of

the MOSFET. The current limit for the converter can be

programmed by:

Current limit = (107mV/RS)(NP/NS) – (1/2)(IRIPPLE)

where:

RS = sense resistor in source of primary MOSFET

IRIPPLE = p-p ripple current in the output inductor L1

NS = number of transformer secondary turns

NP = number of transformer primary turns

Programming Slope Compensation

The LT1952/LT1952-1 use a current mode architecture

to provide fast response to load transients and to ease

frequency compensation requirements. Current mode

switching regulators which operate with duty cycles above

50% and have continuous inductor current must add slope

compensation to their current sensing loop to prevent

subharmonic oscillations. (For more information on slope

compensation, see Application Note 19.) The LT1952/

LT1952-1 have programmable slope compensation to allow

a wide range of inductor values, to reduce susceptibility

to PCB generated noise and to optimize loop bandwidth.

The LT1952/LT1952-1 program slope compensation by

inserting a resistor RSLOPE in series with the ISENSE pin

(Figure 7). The LT1952/LT1952-1 generate a current at

the ISENSE pin which is linear from 0% duty cycle to the

maximum duty cycle of the OUT pin. A simple calculation

of I(ISENSE) • RSLOPE gives an added ramp to the voltage

at the ISENSE pin for programmable slope compensation.

(See both graphs ‘ISENSE Pin Current vs. Duty Cycle’ and

‘ISENSE Maximum Threshold vs Duty Cycle’ in the Typical

Performance Characteristics section.)

CURRENT SLOPE = 35μA • DC

LT1952/

LT1952-1

OUT

OC

ISENSE

1952 F07

RSLOPE

V(ISENSE) = VS + (ISENSE • RSLOPE)

VS

ISENSE = 8μA + 35DC μA

DC = DUTY CYCLE

FOR SYNC OPERATION

ISENSE(SYNC) = 8μA + (k • 35DC)μA

RS k = fOSC/fSYNC

Figure 7. Programming Slope Compensation

19521fd

14

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