LT3579/LT3579-1
APPLICATIONS INFORMATION
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
CIN
–
VIN
+
1
2
3
4
5
6
7
A8
9
10
C
D1
21
C1
20
19
18
17
16
15
14
13 B
12
11
SYNC
SHDN
CLKOUT
GND
COUT
– VOUT
L1
L2
3579 F11
A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
C– RETURN D1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2 – MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.
Figure 11. Suggested Component Placement for Inverting Topology in FE20 Package.
Note Separate Ground Path for D1’s Cathode
35791f
18