LTC1740CG データシートの表示（PDF） - Linear Technology

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LTC1740CG

14-Bit, 6Msps, Sampling ADC

Linear Technology 

LTC1740

APPLICATIO S I FOR ATIO

Full-Scale and Offset Adjustment

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error should be adjusted before full-scale error. Figure 11

shows a method for error adjustment for a dual supply,

5.00V input range application. For zero offset error apply

– 0.15mV (i.␣ e., – 0.5LSB) at + AIN and adjust R1 until the

output code flickers between 00 0000 0000 0000 and 11

1111 1111 1111. For full-scale adjustment, apply an input

voltage of 2.49954V (FS – 1.5LSBs) at + AIN and adjust R2

until the output code flickers between 01 1111 1111 1110

and 01 1111 1111 1111.

Digital Output Drivers

The LTC1740 output drivers can interface to logic operat-

ing from 3V to 5V by setting OVDD to the logic power

supply. OVDD requires a 1µF decoupling capacitor. To

prevent digital noise from affecting performance, the load

capacitance on the digital outputs should be minimized. If

large capacitive loads are required, (>30pF) external buff-

ers or 100Ω resistors in series with the digital outputs are

suggested.

Timing

The conversion start is controlled by the rising edge of the

CLK pin. Once a conversion is started it cannot be stopped

or restarted until the conversion cycle is complete. Output

data is updated at the end of conversion, or about 100ns

after a conversion is begun. There is an additional two

cycle pipeline delay, so the data for a given conversion is

output two full clock cycles plus 100ns after the convert

start. Thus output data can be latched on the third CLK

rising edge after the rising edge that samples the input.

Clock Input

The LTC1740 only uses the rising edge of the CLK pin for

internal timing, and CLK doesn’t necessarily need to have

a 50% duty cycle. For optimal AC performance the rise

time of the CLK should be less than 5ns. If the available

clock has a rise time slower than 5ns, it can be locally sped

up with a logic gate. The clock can be driven with 5V

CMOS, 3V CMOS or TTL logic levels.

5V

R1

50k

–5V

VIN

24k

100Ω

1µF

10k

R2

1k

10k

5V

+AIN

–AIN

LTC1740

VREF

SENSE

VSS

1740 F11

–5V

Figure 11. Offset and Full-Scale Adjust Circuit

1740f

13

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