LTC1742IFW データシートの表示（PDF） - Linear Technology

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LTC1742IFW

14-Bit, 65Msps Low Noise ADC

Linear Technology 

LTC1742

APPLICATIO S I FOR ATIO

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC1742

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(CSAMPLE) through CMOS transmission gates. This direct

capacitor sampling results in lowest possible noise for a

given sampling capacitor size. The capacitors shown

attached to each input (CPARASITIC) are the summation of

all other capacitance associated with each input.

During the sample phase when ENC/ENC is low, the

transmission gate connects the analog inputs to the sam-

pling capacitors and they charge to, and track the differen-

tial input voltage. When ENC/ENC transitions from low to

12

LTC1742

VDD

AIN+

VDD

AIN–

5V

CPARASITIC

4pF

CPARASITIC

4pF

CSAMPLE

4pF

CSAMPLE

4pF

BIAS

2V

6k

ENC

ENC

6k

2V

1742 F02

Figure 2. Equivalent Input Circuit

high the sampled input voltage is held on the sampling

capacitors. During the hold phase when ENC/ENC is high

the sampling capacitors are disconnected from the input

and the held voltage is passed to the ADC core for

processing. As ENC/ENC transitions from high to low the

inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional to

the change in voltage between samples will be seen at this

time. If the change between the last sample and the new

sample is small the charging glitch seen at the input will be

small. If the input change is large, such as the change seen

with input frequencies near Nyquist, then a larger charging

glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential drive

to achieve specified performance. Each input should swing

±0.8V for the 3.2V range or ±0.5V for the 2V range, around

a common mode voltage of 2.35V. The VCM output pin

(Pin␣ 2)maybeusedtoprovidethecommonmodebiaslevel.

VCM can be tied directly to the center tap of a transformer

to set the DC input level or as a reference level to an op amp

differential driver circuit. The VCM pin must be bypassed to

ground close to the ADC with a 4.7µF or greater capacitor.

1742f

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