LTC1742IFW データシートの表示（PDF） - Linear Technology

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LTC1742IFW

14-Bit, 65Msps Low Noise ADC

Linear Technology 

APPLICATIO S I FOR ATIO

LTC1742

5V

CLOCK

INPUT

ANALOG INPUT

0.1µF

1:4

50Ω

VDD

ENC

2V BIAS

6k

VDD

ENC

2V BIAS

6k

LTC1742

BIAS

TO INTERNAL

ADC CIRCUITS

1742 F07

Figure 7. Transformer Driven ENC/ENC

ENC

VTHRESHOLD = 2V

2V ENC LTC1742

0.1µF

1742 F08a

Figure 8a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

3.3V

MC100LVELT22 3.3V 130Ω

Q0

D0

130Ω

ENC

Q0

83Ω

ENC LTC1742

83Ω

1742 F08b

Figure 8b. ENC Drive Using a CMOS-to-PECL Translator

Any noise present on the encode signal will result in

additional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-

cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer

coupled use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a sinusoidal signal, filter the

encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both

encode inputs so that any coupled noise will appear at

both inputs as common mode noise.

The encode inputs have a common mode range of 1.8V to

VDD. Each input may be driven from ground to VDD for

single-ended drive.

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC1742 is 65Msps. For

the ADC to operate properly the encode signal should have

a 50% (±5%) duty cycle. Each half cycle must have at least

7.3ns for the ADC internal circuitry to have enough settling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetric rise and fall times can result in duty cycles that

are far from 50%.

1742f

15

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