LTC1742IFW データシートの表示（PDF） - Linear Technology

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LTC1742IFW

14-Bit, 65Msps Low Noise ADC

Linear Technology 

LTC1742

APPLICATIO S I FOR ATIO

OVDD can be powered with any voltage up to 5V. The logic

outputs will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE low disables all data outputs including OF and

CLKOUT. The data access and bus relinquish times are too

slow to allow the outputs to be enabled and disabled

during full speed operation. The output Hi-Z state is

intended for use during long periods of inactivity. The

voltage on OE can swing between GND and OVDD. OE

should not be driven above OVDD.

GROUNDING AND BYPASSING

The LTC1742 requires a printed circuit board with a clean

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. The pinout of the

LTC1742 has been optimized for a flowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as

shown in the block diagram on the front page of this data

sheet. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-

tors between REFHA and REFLB and between REFHB and

REFLA. These capacitors should be as close to the device

as possible (1.5mm or less). Size 0402 ceramic capacitors

are recomended. The large 4.7µF capacitor between REFHA

and REFLA can be somewhat further away. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The LTC1742 differential inputs should run parallel and

close to each other. The input traces should be as short as

possible to minimize capacitance and to minimize noise

pickup.

An analog ground plane separate from the digital process-

ing system ground should be used. All ADC ground pins

labeled GND should connect to this plane. All ADC VDD

bypass capacitors, reference bypass capacitors and input

filter capacitors should connect to this analog plane. The

LTC1742 has three output driver ground pins, labeled

OGND (Pins 27, 38 and 47). These grounds should con-

nect to the digital processing system ground. The output

driver supply, OVDD should be connected to the digital

processing system supply. OVDD bypass capacitors should

bypass to the digital system ground. The digital process-

ing system ground should be connected to the analog

plane at ADC OGND (Pin 38).

HEAT TRANSFER

Most of the heat generated by the LTC1742 is transferred

from the die through the package leads onto the printed

circuit board. In particular, ground pins 12, 13, 36 and 37

are fused to the die attach pad. These pins have the lowest

thermal resistance between the die and the outside envi-

ronment. It is critical that all ground pins are connected to

a ground plane of sufficient area. The layout of the evalu-

ation circuit shown on the following pages has a low ther-

mal resistance path to the internal ground plane by using

multiple vias near the ground pins. A ground plane of this

size results in a thermal resistance from the die to ambient

of 35°C/W. Smaller area ground planes or poorly connected

ground pins will result in higher thermal resistance.

1742f

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