LTC1746C データシートの表示（PDF） - Linear Technology

部品番号

コンポーネント説明

メーカー

LTC1746C

Low Power,14-Bit, 25Msps ADC

Linear Technology 

LTC1746

DIGITAL I PUTS A D DIGITAL OUTPUTS The q indicates specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

VIH

High Level Input Voltage

VDD = 5.25V

q 2.4

V

VIL

Low Level Input Voltage

VDD = 4.75V

q

0.8

V

IIN

Digital Input Current

VIN = 0V to VDD

q

±10

µA

CIN

Digital Input Capacitance

MSBINV and OE Only

1.5

pF

VOH

High Level Output Voltage

OVDD = 4.75V

IO = –10µA

4.74

V

IO = – 200µA q 4

V

VOL

Low Level Output Voltage

OVDD = 4.75V

IO = 160µA

0.05

V

IO = 1.6mA q

0.1

0.4

V

IOZ

Hi-Z Output Leakage D13 to D0

VOUT = 0V to VDD, OE = High

q

±10

µA

COZ

Hi-Z Output Capacitance D13 to D0

OE = High (Note 8)

q

15

pF

ISOURCE Output Source Current

VOUT = 0V

– 50

mA

ISINK

Output Sink Current

VOUT = 5V

50

mA

POWER REQUIRE E TS The q indicates specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

VDD

IDD

PDIS

OVDD

Positive Supply Voltage

Positive Supply Current

Power Dissipation

Digital Output Supply Voltage

2V Range, Full-Scale Input

2V Range, Full-Scale Input

4.75

5.25

V

q

78

93

mA

q

390

465

mW

0.5

VDD

V

WU

TI I G CHARACTERISTICS The q indicates specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

fSAMPLE

t1

t2

t3

t4

t5

t6

t7

t8

Sampling Frequency

ENC Low Time

ENC High Time

Aperture Delay of Sample-and-Hold

ENC to Data Delay

ENC to CLKOUT Delay

CLKOUT to Data Delay

DATA Access Time After OE ↓

BUS Relinquish Time

Data Latency

(Note 9)

(Note 9)

(Note 9)

(Note 8)

CL = 10pF (Note 8)

CL = 10pF (Note 8)

CL = 10pF (Note 8)

CL = 10pF (Note 8)

(Note 8)

q1

q 19

q 19

q 1.4

q 0.5

q0

25

MHz

20

1000

ns

20

1000

ns

0

ns

4

10

ns

2

5

ns

2

ns

10

25

ns

10

25

ns

5

cycles

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND

(unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND, they will be

clamped by internal diodes. This product can handle input currents of

>100mA below GND without latchup. These pins are not clamped to VDD.

Note 5: VDD = 5V, fSAMPLE = 25MHz, differential ENC/ENC = 2VP-P 25MHz

sine wave, input range = ±1.6V differential, unless otherwise specified.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB

when the output code flickers between 00 0000 0000 0000 and 11

1111 1111 1111.

Note 8: Guaranteed by design, not subject to test.

Note 9: Recommended operating conditions.

1746f

4

Share Link: