LTC2246LX(RevB) データシートの表示（PDF） - Linear Technology

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LTC2246LX
(Rev.:RevB)

14-Bit, 25Msps 125°C ADC In LQFP

Linear Technology 

LTC2246H

APPLICATIONS INFORMATION

Data Format

Using the MODE pin, the LTC2246H parallel digital output

can be selected for offset binary or 2’s complement format.

Connecting MODE to GND or 1/3VDD selects offset binary

output format. Connecting MODE to 2/3VDD or VDD selects

2’s complement output format.

An external resistor divider can be used to set the 1/3VDD

or 2/3VDD logic values. Table 2 shows the logic states for

the MODE pin.

Table 2. MODE Pin Function

MODE PIN

0

1/3VDD

2/3VDD

VDD

OUTPUT FORMAT

Offset Binary

Offset Binary

2’s Complement

2’s Complement

CLOCK DUTY

CYCLE STABILIZER

Off

On

On

Off

Overflow Bit

When OF outputs a logic high the converter is either over-

ranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven.

For example if the converter is driving a DSP powered

by a 1.8V supply, then OVDD should be tied to that same

1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND

up to 1V and must be less than OVDD. The logic outputs

will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE high disables all data outputs including OF.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to VDD and OE to VDD

results in sleep mode, which powers down all circuitry

including the reference and typically dissipates 1mW. When

exiting sleep mode it will take milliseconds for the output

data to become valid because the reference capacitors

have to recharge and stabilize. Connecting SHDN to VDD

and OE to GND results in nap mode, which typically dis-

sipates 15mW. In nap mode, the on-chip reference circuit

is kept on, so that recovery from nap mode is faster than

that from sleep mode, typically taking 100 clock cycles. In

both sleep and nap modes, all digital outputs are disabled

and enter the Hi-Z state.

Grounding and Bypassing

The LTC2246H requires a printed circuit board with a clean,

unbroken ground plane. A multilayer board with an internal

ground plane is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

tors must be located as close to the pins as possible. Of

particular importance is the 0.1μF capacitor between REFH

and REFL. This capacitor should be placed as close to the

device as possible (1.5mm or less). A size 0402 ceramic

capacitor is recommended. The large 2.2μF capacitor be-

tween REFH and REFL can be somewhat further away. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

The LTC2246H differential inputs should run parallel and

close to each other. The input traces should be as short

as possible to minimize capacitance and to minimize

noise pickup.

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