LTC2264UJ-14(RevB) データシートの表示（PDF） - Linear Technology

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LTC2264UJ-14
(Rev.:RevB)

14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2265-14/

LTC2264-14/LTC2263-14

APPLICATIONS INFORMATION

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12 and 13).

The encode inputs are internally biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

above VDD (up to 3.6V), and the common mode range

is from 1.1V to 1.6V. In the differential encode mode,

ENC– should stay at least 200mV above ground to avoid

falsely triggering the single-ended encode mode. For

good jitter performance ENC+ should have fast rise and

fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

encode input. ENC+ can be taken above VDD (up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The

ENC+ threshold is 0.9V. For good jitter performance

ENC+ should have fast rise and fall times.

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

DIGITAL OUTPUTS

The digital outputs of the LTC2265-14/LTC2264-14/

LTC2263-14 are serialized LVDS signals. Each channel

outputs two bits at a time (2-lane mode) or one bit at a time

(1-lane mode). The data can be serialized with 16-, 14-, or

12-bit serialization (see the Timing Diagrams section for

details). Note that with 12-bit serialization the two LSBs

are not available—this mode is included for compatibility

with the 12-bit versions of these parts.

The output data should be latched on the rising and falling

edges of the data clockout (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversion result begins. In the 2-lane, 14-bit serialization

mode, the frequency of the FR output is halved.

The maximum serial data rate for the data outputs is

1Gbps, so the maximum sample rate of the ADC will de-

pend on the serialization mode as well as the speed grade

of the ADC (see Table 1). The minimum sample rate for

all serialization modes is 5Msps.

0.1µF T1

50Ω

0.1µF

50Ω

ENC+ LTC2265-14

100Ω

0.1µF

ENC–

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

Figure 12. Sinusoidal Encode Drive

226514 F12

PECL OR

LVDS

CLOCK

0.1µF

ENC+

0.1µF

ENC–

LTC2265-14

226514 F13

Figure 13. PECL or LVDS Encode Drive

22654314fb

21

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