LTC2903IS6-B1 データシートの表示（PDF） - Linear Technology

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LTC2903IS6-B1

Precision Quad Supply Monitor in 6-Lead SOT-23

Linear Technology 

LTC2903-1

APPLICATIO S I FOR ATIO

In any supervisory application, supply noise riding on the

monitored DC voltage can cause spurious resets, particu-

larly when the monitored voltage approaches the reset

threshold. A less than desirable but commonly used

technique used to mitigate this problem adds hysteresis to

the input comparator. The amount of added hysteresis,

usually specified as a percentage of the trip threshold,

effectively degrades the advertised accuracy of the part.

To maintain high accuracy, the LTC2903-1 does not use

hysteresis.

To minimize spurious resets while maintaining threshold

accuracy, the LTC2903-1 employs two forms of noise

filtering. The first line of defense incorporates proprietary

tailoring of the comparator transient response. Transient

events receive electronic integration in the comparator

and must exceed a certain magnitude and duration to

cause the comparator to switch. Figure 5 illustrates the

typical transient duration versus comparator overdrive

(as a percentage of the trip threshold VRT) required to trip

the comparators. Once any comparator is switched, the

reset line pulls low. The reset time-out counter starts once

all inputs return above threshold. The nominal reset delay

time is 200ms. The counter clears whenever any input

400

TA = 25°C

350

300

250

200

RESET OCCURS

ABOVE CURVE

150

100

50

0

0.1

1

10

100

RESET COMPARATOR OVERDRIVE (% OF VRTX)

29031 F05

Figure 5. Typical Transient Duration vs Overdrive

Required to Trip Comparator

drops back below threshold. This reset delay time effec-

tively provides further filtering of the voltage inputs. A

noisy input with frequency components of sufficient mag-

nitude above f = 1/tRST = 5Hz holds the reset line low,

preventing oscillatory behavior on the reset line.

Although all four comparators have built-in glitch filtering,

use bypass capacitors on the V1 and V2 inputs because

the greater of V1 or V2 supplies the VCC for the part (a

0.1µF ceramic capacitor satisfies most applications). Ap-

ply filter capacitors on the V3 and V4 inputs in extremely

noisy situations.

Reset Output Rise and Fall Time Estimation

The reset output line contains a weak pull-up current

source to the V2 supply. Use an external pull-up resistor

when the output needs to pull to another voltage and/or

when the reset output needs a faster rise time. The open-

drain output allows for wired-OR connections when more

than one signal needs to pull down on the reset line.

Estimate output rise time for the open-drain output with-

out an external pull-up using:

tRISE ≈ 2.2 • RPU • CLOAD

where RPU is the on-resistance of the pull-up transistor

and CLOAD is the external load capacitance on the pin. At

room temperature, the average RPU is approximately

50kΩ. When externally pulling up to voltages higher than

V2, an internal network automatically protects the weak

pull-up circuitry from reverse currents.

The reset output has very strong pull-down capability.

Estimate the output fall time using:

tFALL ≈ 2.2 • RPD • CLOAD

where RPD is the on-resistance of the pull-down transistor

and CLOAD is the external load capacitance on the pin. At

room temperature, the average RPD is approximately 40Ω.

With a 150pF load capacitance the reset line can pull down

in about 13ns.

29031f

12

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