LTC2924C(RevA) データシートの表示（PDF） - Linear Technology

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LTC2924C
(Rev.:RevA)

Quad Power Supply Sequencer

Linear Technology 

LTC2924

APPLICATIO S I FOR ATIO

Minimize stray capacitance on the ON and IN1-IN4 pins.

As a practical matter, lay out these resistors as close to

the LTC2924 as possible.

Details of Resistor Calculations

In this example, the voltage at the IN pins is 0.61V when the

LTC2924 detects that the power supply is On during a Power

On sequence or Off during a Power Off sequence.

The delta voltage, ΔV, represents the difference:

ΔV = 2.2V – 1V = 1.2V

This delta voltage on RB will be equal to the product of

hysteresis current IHYS and RB. Therefore:

RB

=

∆V

IHYS

=

1.2V

50µA

=

24kΩ

The current IRB at the Power On voltage of 2.2V is:

IRB

=

2.2V – 0.61V

24k

=

66µA

During the Power On sequence, IHYS = 0, so IFB is equal

to IRB and RA is:

RA

=

0.61

66µA

=

9.2k

VOFF Precaution

Use caution if designs call for VOFF voltages less than ~0.8V.

Many loads stop using significant current at this level, and

the power supply may take a long time to go below this

voltage. If VOFF voltages at or less than this voltage are

necessary, consider adding an extra resistive load at the

output of the power supply to ensure it discharges in a

reasonable amount of time.

Selecting the Timing Capacitor

During the Power On sequence, the timer is used to cre-

ate a delay between the time one supply reaches the On

threshold and the next supply is enabled. During the Power

Off sequence, the timer is used to create a delay between

the time one supply reaches the Off threshold and the

next supply is disabled. Select the timing capacitor with

the following equation:

CTMR [µF] = tDELAY • 5µF/s

Leaving the TMR pin unconnected will generate the mini-

mum delay. The accuracy of the time delay will be affected

by the capacitor leakage (the nominal charge current is

5µA) and capacitor tolerance. A low leakage ceramic

capacitor is recommended.

Selecting the Power Good Timer (PGT) Capacitor

During the Power On sequence, the PGT can be used to

detect the failure of a power supply to reach the desired

On voltage. The PGT is enabled each time a power supply

is enabled by the OUT1-OUT4 pins. The PGT is reset each

time an IN1-IN4 pin detects that a power supply is at the

desired On voltage. Select the PGT timeout capacitor with

the following equation:

CPGT [µF] = tPGT • 5µF/s

If no PGT is desired, the PGT pin must be shorted to

ground. The accuracy of the PGT timeout will be affected

by the capacitor leakage (the nominal charge current

is 5µA) and capacitor tolerance. A low leakage ceramic

capacitor is recommended.

2924fa

11

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