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LTC3541

High Efficiency Buck + VLDO Regulator

Linear Technology 

LTC3541

APPLICATIONS INFORMATION

and proportional to frequency. Both the DC bias

and gate charge losses are proportional to VIN and

thus their effects will be more pronounced at higher

supply voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In con-

tinuous mode, the average output current flowing through

inductor L is “chopped” between the main switch and the

synchronous switch. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses, simply add RSW to

RL and multiply the result by the square of the average

output current.

3. Losses in the VLDO/linear regulator are due to the DC bias

currents as given in the Electrical Characteristics and to the

(VIN – VOUT) voltage drop across the internal output device

transistor.

Other losses when the buck and VLDO are in operation

(ENBUCK and ENVLDO equal logic high), including CIN

and COUT ESR dissipative losses and inductor core losses,

generally account for less than 2% total additional loss.

THERMAL CONSIDERATIONS

The LTC3541 requires the package backplane metal (GND

pin) to be well soldered to the PC board. This gives the

DFN package exceptional thermal properties. The power

handling capability of the device will be limited by the

maximum rated junction temperature of 125°C. The

LTC3541 has internal thermal limiting designed to protect

the device during momentary overload conditions. For

continuous normal conditions, the maximum junction

temperature rating of 125°C must not be exceeded. It is

important to give careful consideration to all sources of

thermal resistance from junction to ambient. Additional

heat sources mounted nearby must also be considered.

For surface mount devices, heat sinking is accomplished

by using the heat-spreading capabilities of the PC board

and its copper traces. Copper board stiffeners and plated

through holes can also be used to spread the heat gener-

ated by power devices.

To avoid the LTC3541 exceeding the maximum junction

temperature, some thermal analysis is required. The goal

of the thermal analysis is to determine whether the power

dissipated exceeds the maximum junction temperature of

the part. The temperature rise is given by:

TR = PD • qJA

where PD is the power dissipated by the regulator and qJA

is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

TJ = TA + TR

where TA is the ambient temperature.

As an example, consider the LTC3541 with an input voltage

VIN of 2.9V, an LVIN voltage of 1.8V, an LVOUT voltage of

1.5V, a load current of 200mA for the buck, a load current

of 300mA for the VLDO and an ambient temperature of

85°C. From the typical performance graph of switch re-

sistance, the RDS(ON) of the P-channel switch at 85°C is

approximately 0.25Ω.The RDS(ON) of the N-channel switch

is approximately 0.4Ω. Therefore, power dissipated by the

part is approximately:

PD = (ILOADBUCK)2 • RSW + (ILOADVLDO) •

(LVIN – LVOUT) = 167mW

For the 3mm × 3mm DFN package, the qJA is 43°C/W.

Thus, the junction temperature of the regulator is:

TJ = 85°C + (0.167)(43) = 92°C

which is well below the maximum junction temperature

of 125°C.

Note that at higher supply voltages, the junction tempera-

ture is lower due to reduced switch resistance RDS(ON).

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For more information www.linear.com/LTC3541

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