LTC6991HS6 データシートの表示（PDF） - Linear Technology

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LTC6991HS6

TimerBlox: Resettable, Low Frequency Oscillator

Linear Technology 

LTC6991

Operation

Changing DIVCODE After Start-Up

Following start-up, the A/D converter will continue

monitoring VDIV for changes. The LTC6991 will respond

to DIVCODE changes in less than one cycle.

tDIVCODE < 500 • tMASTER < tOUT

The output may have an inaccurate pulse width during the

frequency transition. But the transition will be glitch-free

and no high or low pulse can be shorter than the mas-

ter clock period. A digital filter is used to guarantee the

DIVCODE has settled to a new value before making changes

to the output.

Start-Up Time

When power is first applied, the power-on reset (POR)

circuit will initiate the start-up time, tSTART . The OUT pin

is held low during this time. The typical value for tSTART

ranges from 0.5ms to 8ms depending on the master oscil-

lator frequency (independent of NDIV):

tSTART(TYP) = 500 • tMASTER

During start-up, the DIV pin A/D converter must determine

the correct DIVCODE before the output is enabled. The

start-up time may increase if the supply or DIV pin volt-

ages are not stable. For this reason, it is recommended to

minimize the capacitance on the DIV pin so it will properly

track V+. Less than 100pF will not affect performance.

Start-Up Behavior

When first powered up, the output is held low. If the po-

larity is set for non-inversion (POL = 0) and the output is

enabled (RST = 0) at the end of the start-up time, OUT will

begin oscillating. If the output is being reset (RST = 1) at

the end of the start-up time, the first pulse will be skipped.

Subsequent pulses will also be skipped until RST = 0.

In inverted operation (POL = 1), the start-up sequence is

similar. However, the LTC6991 does not know the correct

DIVCODE setting when first powered up, so the output

defaults low. At the end of tSTART , the value of DIVCODE is

recognized and OUT goes high (inactive) because POL = 1.

If RST = 1 (inactive) then OUT will quickly fall after a single

tMASTER cycle. If RST = 0 at the end of the start-up time,

the output is held in reset and remains high.

Figures 7 to 10 detail the four possible start-up sequences.

DIV

200mV/DIV

OUT

1V/DIV

V+ = 3.3V

RSET = 200k

10ms/DIV

6991 F05

Figure 5. DIVCODE Change from 1 to 0

V+

1V/DIV

OUT

1V/DIV

500µs

V+ = 2.5V

DIVCODE = 0

RSET = 50k

250µs/DIV

6991 F06

Figure 6. Typical Start-Up

6991f

12

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