LTC6991
Applications Information
Basic Operation
The simplest and most accurate method to program the
LTC6991 is to use a single resistor, RSET , between the SET
and GND pins. The design procedure is a 3-step process.
First select the POL bit setting and NDIV value, then calculate
the value for the RSET resistor.
Step 1: Select the POL Bit Setting
The LTC6991 can operate in normal (active-high) or inverted
(active-low) modes, depending on the setting of the POL
bit. The best choice depends on the the application.
Step 2: Select the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given output clock period, NDIV should
be selected to be within the following range.
tOUT
16.384ms
≤
NDIV
≤
tOUT
1.024ms
(1)
To minimize supply current, choose the lowest NDIV value
(generally recommended). Alternatively, use Table 1
as a guide to select the best NDIV value for the given
application.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET
=
50k
1.024ms
•
tOUT
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a 1Hz oscillator with minimum power
consumption and active-high reset input.
Step 1: Select the POL Bit Setting
For noninverted (active-high) functionality, choose
POL = 0.
Step 2: Select the NDIV Frequency Divider Value
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 1000ms:
61.04 ≤ NDIV ≤ 976.6
Potential settings for NDIV include 64 and 512. NDIV = 64
is the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 0 and NDIV = 64 requires
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
Step 3: Select RSET
Calculate the correct value for RSET using Equation (2).
RSET
=
50k
1.024ms
•
1000ms
64
=
763k
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
The completed design is shown in Figure 11.
RST RST
OUT
LTC6991
2.25V TO 5.5V
GND
V+
SET
DIV
RSET
763k
R1
976k
DIVCODE = 2
R2
182k
6991 F11
Figure 11. 1Hz Oscillator
6991f
14